Motorola 88100 CPU
Used in
Details
- Four functional units, fully independent with five concurrent pipelines
- Up to 33MHz clock frequency
- 32 general purpose registers
- Harvard-style bus-structure,
- Separate data and instruction memory ports
- 30-bit data address bus
- 32-bit data bus
- 30-bit instruction address bus
- 32-bit instruction bus
- Pipelined load/store operations
- Selectable Big-Endian or Little-Endian Byte-ordering
- Extensible through optional Special Function Units (SFUs)
- L1 cache is external to the CPU and provided by the so-called 88200/88204
cache/memory management units (CMMUs), available in different sizes
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