Motorola 88200/4 CMMU

This is the cache/memory management unit (CMMU) for systems with the original 88100 CPU. It implements demand-paged virtual memory management with a 16KB cache memory (64KB on 88204) on a VLSI chip. To implement the maximum of 256KB/256KB I/D cache on a 88100 system, eight 88204 CMMUs had to be used. It was also possible to build a system without any CMMU at all, as done e.g. on several embedded systems, which resulted in a system unable to use VM.

Details

• Two logical 4GB address spaces
• 16KB cache on 88200, 64KB cache on 88204, four-way set-associative
• Cache-accesses are zero-wait-state
• Least Recently Used (LRU) replacement algorithm
• Either copy-back or write-through cache policy
• Cache consistency with other caches and main memory provided by a bus-snoop protocol
• Memory bus is parity protected
• HCMOS

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