Motorola 88110 CPU

Used in

• Data General AViiON AV500, AV550, AV4500, AV5500, AV8500+, AV9500+
• MVME197LE
• MVME197SP and MVME197DP
• Motorola Delta Series 95xx and 99xx
• Motorola Series 900 Model 921 (MVME197-based)
• Motorola Series 900 Model 922 (MVME197-based)
• Motorola XR Series 900 Model XR9109
• Motorola XR Series 900 Model XR9209
• NeXTstation RISC Prototype
• Tadpole TP810V

The 88110 was the second generation member of the 88000 family and the direct successor to the 88100 CPU. It basically integrated the functions of the 88100 CPU and the 88200 CMMU into one single chip. Supposedly three to five times faster than its predecessor, it featured several enhancements to the architecture besides the above-mentioned chip-integration.

It is the first superscalar implementation of the m88k architecture. A FP register-file and new graphics instructions were introduced. Up to two instructions can be dispatched to the ten functional units, stores and branches can be issued out-of-order, the instruction path is speculatively executed beyond conditional branches. All functional units, except the divide unit, are able to receive a new instruction every single clock cycle. The instruction unit of the 88110 is the main unit which controls the instruction and data flow; it performs fetching, decoding and issueing of the instructions and is able to process two instructions on every cycle.

Three types of system configurations were targeted:

1. Single-processor, closely coupled to DRAM.
2. Dual-processor, also closely coupled to DRAM. Variants should have included both SMP style arrangemants or AMP, so that one 88110 is a dedicated processor for particular functions, as e.g. graphics or DSP.
3. Medium-scale shared-memory multiprocessor systems with big local L2 caches.

Details

• 10 functional units:
  • 2 integer ALUs (32-bit operands)
  • 1 FP-add (80-bit operands)
  • 1 multiply (64-bit integer, 80-bit FP operands)
  • 1 divide (64-bit integer, 80-bit FP operands)
  • 1 bit-field (32-bit operands)
  • 1 instruction/branch
  • 1 data-cache
  • 2 graphics (64-bit operands)
• 2 instructions can be fetched, decoded and issued per cycle.
• up to 50MHz clock frequency
• SMP-capable
• 32 32-bit integer registers
• 32 80-bit FP registers
• on-chip L1 I-cache: 8KB, 32-Byte line size, 2-way set associative, physically addressed software I-cache coherency.
• on-chip L1 D-cache: 8KB, 32-Byte line size, 2-way set associative, physically addressed, either write-through or write-back, non-blocking, MESI cache coherency
• offchip L2 cache controlled by 88410
• cache line are filled and emptied using 8-word burst transfers
• load instruction buffers queue load instructions waiting for the cache
• 64-bit wide cache and data bus datapath
• 32-bit wide address-bus
• TLB: 32/32 page-entry I/D, 4KB page size, fully associative, FIFO or software replacement
  8/8 block-entry, up to 64MB block size, fully associative, software replacement
• stores and branches are executed out-of-order (OoO)
• static branch prediction
• 12-entry history buffer for register written due to mispredicted branches
• 32-entry BTAC (Branch Target Address Cache)
• symmetric issuing — no restrictions on address alignment or types
• binary compatible to predecessors
• 1,400,000 FETs, 0.8 micron HCMOS, packaged in a 299-pin PGA
• SPEC92 int/fp: 51.0/73.9

References

• MC88110 Overview from Mark Smotherman. Apr. 1994
• MC88110 Second Generation RISC Microprocessor User's Manual (MC88110UM) (.pdf, 51MB)

↑ up